Current consumption? Power consumption?

At this core board current consumption abnormal high issue,
When we apply DC3.3V to core, the current consumption is 350mA, whereas the former MaChao whole system current consumption is just 160mA. We are in facking PANIC!!

Try to decrease by-pass capacitor; lower the floating I/O pin current consumption; PCB layout issue; ferrite beads internal resistance too high; resistors of the voltage ladder provide Vref of DDR too low; and many other facking guess...all in FACKING VAIN!!

Finally, we find someone who knows power well(he is a facking good power chip designer!!). He told us not just see the current consumption, we should consider the POWER CONSUMPTION!!

Do some simple calculation, the former Machao system is DC12V supply and 160mA current consumption, thus the power consumption is 12*0.16=1.92(W). Then for core board is DC3.3V supply and 350 current consumption, thus the power consumption is 3.3*0.35=1.155(W). Well, the power consumption seems a facking reasonable way.

Then I do a experiment, build a voltage regulate board which is DC12V to DC3.3V, the core board apply the DC3.3V from the regulation board. Then we can see the current consumption is low to 100mA by DC12V source. Perfect!!

During this issue, we learned about not only the current consumption, the power consumption is needed to be considered. The P=VI equation is really FACKING IMPORTANT!!

Heterodyne

Heterodyne comes from the Greek root hetero-"different" and -dyne"power".

In radio and signal processing, heterodyne is the generation of new frequencies by mixing or multiplying two oscillating waveforms. It is useful for modulation and demodulation of signals, or placing information of interest into a useful frequency range.

Mixing two frequencies creates two new frequencies, one at the sum of the two frequencies mixed, and the other at their difference. Typically only one of these frequencies is desired--the higher one after modulation and the lower one after demodulation. The other signal is either not passed by the tuned circuitry follows or may be filtered out.

購屋體檢表

以下尻背從"實踐家與夢想家"網站

===============================================
銀行評斷物件的貸款成數絕大部分會因其條件優劣而作決定,
m1 D/ A# M: x* N& y' S! h銀行的所指的A,B,C,D區便是房子好壞,貸款成數高低的行內用語.
" N& Y2 d7 I; R+ [ f2 o: H一般人要如何選擇房子才不會落入銀行判定為C或D區的可憐命運呢?
4 P( J4 j& F2 r* }4 L; O. d簡單的說就是,"適合人類居住的房子,就是銀行喜歡的物件"!!* D9 L* P9 i2 e* L! e( u& o; ^
有人會說,這樣講不是等於沒講!?
8 E! |: c: I: K其實這是事實,一個房子住的很舒服都有其原因,
5 ]9 U+ F3 z! M1 C9 H3 _8 u C) M只是人們沒有去特別注意而已.
8 s8 D- B7 G- T) N7 o1 f4 R Y# y- @- g8 i4 ?; Y- O* Q) ]1 k; a

以下內容需要回復才能看到

我有一位朋友他有一次跟我提到,他的哥哥最近想買房子,
0 X, P% U- ~. T# `我問他你哥哥是怎麼決定選擇一間房子的?/ t0 I0 n$ u5 q9 F+ X5 P* b
他說:我哥哥每當走進一間房子時," Q3 v+ ~& J2 n8 s
如果喜歡就會有感覺,那種感覺會讓他有想買的衝動....
- K8 P$ a9 n1 s! G# g
# B; i, L6 f/ \感覺?好像靈異節目的說辭,不過他的話也不是完全不對,
' P. _" `1 x$ U3 r4 z( u; e如果是行家,感覺會是理性判斷下的產物;
. T W$ w& A) E, Z' a- Y) L若你只是一個單純的購屋族,
0 \' k. S& d8 ]感覺很有可能會是美輪美奐的裝潢,; s/ l' l2 n9 s8 [' M: y
或是很美麗的海景,但,你的工作可能只適合出海捕魚...* F( c+ {% v; v) `1 X% l' U& f

. e" g% d# g! ?. i7 k) \4 a/ [其實買房子可以更理性點,更科學點,更精準點,1 U8 b- n4 R+ s9 b
那些感覺會建立在以下的條件...1 {) O: i% g0 i; Y) y M" F: h8 Y
8 _& M- p) A- z
(p.s.1若你是房子投資客重度玩家,有些條件可能不適合你,如有些投資客會選住辦混和或工業住宅)
! w5 V0 q; Z0 `( @8 h(p.s.2 此表非完整或完全正確表格,歡迎各位實踐家與夢想家的團隊們一起集思廣益,將此表修正的更加完整,以後此表再配合從Trump老師那裡所習得的估價,貸款,及談判技巧,想買到不好或貴的物件,除非你是從小立志作潘仔腳的人了!)
( V9 U! I p9 i. U( z! B. \5 q" m/ M/ D3 n8 @
加分項目 % @ U3 x% ~- S" c9 [7 R9 O5 O
好地段
5 t& [8 z" I; f1 P7 d' J$ i K# u純住宅非住辦混合 ( @/ ~, b0 A5 _) k. p* Q
有公園綠地 / r% z# F3 f9 X3 Q6 R9 H9 d
有山林景觀
; D: b' N$ R4 p2 \- n) J為人文薈萃之地 ' z2 d2 {! X& Y( f6 N, e
附近有明星國小中學學區 # g: d# d2 K; O4 t
位於安靜住宅區 * G* U1 I( c- @3 P) z
走路5分鐘便可獲得食衣住行滿足的商圈 8 ?8 I+ ~/ Z7 c- R) g u2 p
走路3分鐘內有便利超商
5 X$ d, g8 [9 p c9 n9 j w發生火災時消防車或警察可在三分鐘內到達 1 m, Z7 m0 W6 o/ U3 s0 B
有公車在步行五分鐘內 # t0 L8 i" b# N: v" R, B; ]8 `7 ^
有捷運在步行五分鐘內
7 p/ I/ i9 ?2 B( ]( X4 r% H好停車停車位未飽和(以非供過於求的住宅區為前提) ; E- v& w# h& \1 V: ` a
有聯外道路 % A/ K! S) y2 Y+ u" X8 s
夜間點燈數有五成以上
! [! \6 |8 p* z3 L$ g公設比例合理
1 H" c b8 H) T0 `# |格局方正
# O" M" `& O% i+ P/ s沒有閒置浪費的坪數
1 W! A! c/ ^% @/ h( Y" {室內動線順暢
# k7 r$ F9 E8 N. j( k* w2 k. k沒有因風水問題而需另裝潢
6 ~. K, {2 N' U* m8 I; s採光良好,或裝潢可改善
% R, _; Z& J" z( F4 E: `7 `3 a是邊間的房子
. R0 ? }* k, \; E5 q座北朝南的房子,沒有日曬的問題
3 @5 n/ w, ?9 E/ f通風良好
( K" `+ O$ p% D" j8 ]6 D是高樓層 2 l4 M" C0 i9 {2 P* v
是好門牌 ' L5 w3 S; N4 F8 S. n
有廣告牆可用(投資用參考) 7 F" X) t2 Q1 A
民國84年以前的頂加(投資用參考) 2 e2 H1 l. d& O; C" ]

2 F. G) Z0 O& g5 ^& e扣分項目 0 ^+ R3 E8 N# s/ d- U
有高壓電塔
2 \0 m) ]$ Q4 t4 |是工業區住宅 / C0 @) N# P8 O7 V
有聲色行業
. {6 g9 E c" [- V有網咖ktv八大行業 5 N! g3 D0 K2 v' B& d
附近有攤販 1 H- Z. N E# l5 d5 g- [
附近有寺廟 ) Q$ E0 Q* {- w( @1 ^# M3 u- h
附近有墳墓
( ?9 q! T s" s- V/ F* a有噪音源 6 n- Z4 d8 V, `+ Q
有污染源
7 w" W# b* I& }% T. S) P地板傾斜
* m: J' j8 o% [$ [1 C1 t凶宅
# D+ N9 ]* S& s9 p |1 Z" m( e0 T海砂屋 4 }; E8 x: D9 H0 F) T
輻射屋
; `0 N# W* `% T2 m# P地段不好 ]- v8 K: R" P& E9 C( h) f% Q+ c
房子在電箱旁 : a* p4 v) m" J
L0 x2 i' t+ p f+ T

& [% d# q# W/ a* c1 M% ~+ a/ P以下條件較偏向純自住所需考量 3 G8 c" z6 M+ @ w2 y3 }* E
住戶水準優良
, R; L4 ^% p$ p5 h# W" A. S( N管理委員會完善
1 d3 E& y8 m, U- l2 X+ E出入口有管制人員 $ m. T2 G3 M, C3 k& w) n) R/ }
管理費用合理 7 S6 x# [: {/ F) k% ?! a! v. ^
公設使用率高維護良好
4 b% D8 R4 \& l公設距離近 4 A. S8 j: ]# z5 f1 }$ \- h, K
公設使用不需另行付費
* o: I/ F C9 a( [% H$ k; _- @牆壁不會漏水
) n) s* m1 V% e牆壁沒有壁癌
5 F+ R; M! k6 {8 \5 X* E1 \沒有水泥裂縫
% P$ W6 t; s) ?' J) U+ Q" Y" a7 r& G樓梯間老舊
% U; w7 S) _: \3 L有天然瓦斯
/ j9 [+ L( D5 r8 s衛浴設備不需整修
}8 w2 N: |* h# B7 E) T0 D電壓足夠
" `& W# r0 I# l水壓足夠 . e; U f; W" P
水電沒有被偷接
; m3 |. i f& @' X' T; W9 r不是塞車路段(若是好地段造成的堵車則不適用)
7 u% K8 u( m$ A& m. r, m3 o- B' B, X: b2 r5 }2 A

7 ^3 |" X1 V2 t x0 ]; o; l3 c簡單風水參考(扣分項目)(風水見人見智但有時重大風水亦為銀行評判考量)
" I& ^5 q$ W7 W8 _5 `處於道路或河流反弓處 ' F0 H% R1 x4 u2 d7 A! C: ^' j
非方形地基
( {. X6 \+ W4 N- S# ?地基前寬後窄 4 T, }) h1 R: J" e7 d# [5 T! }+ d4 p
房子對到別人的屋角 7 e! o% u' Z: X) a8 }% b
門前正對地下停車場出口 ' I* D: x' r0 I' H6 D" t
有暗房
! f$ h+ e" ?2 ^, E大門正對樓梯 5 y$ l: y- E) y: H7 f1 k) q
房間門對房間門
M0 N; u J3 B: Z `1 k房間上方有重樑壓頂 ( p% p$ r7 v# K# ]6 z7 H
廚房採開放式設計
3 G) N: Q& U& N' v廁所位於大門邊或整個房子中間
$ r# |3 g Y8 n) _1 Q+ b房門為餘屋子三個角落 # u: o/ G0 _+ B% C O
打開大門可直接看到後門
7 W6 \& l# u6 V, S地基缺角1/3以上
: g7 F. W% S# D$ b位於死巷裡 1 B8 [0 j4 M7 l
房屋地基低於路面
3 w. {0 s# w+ x! N) P% q3 j% t5 N9 l, o天橋,陸橋,高架橋切過建築物
6 g& j- s" R) K4 E, \& m4 o房子蓋在山坡上
6 ` k* ^1 p. [1 O$ k& t6 l面對兩棟大樓的縫隙
7 P0 ~1 L% w/ f& [) b: N7 E3 u正對馬路(路衝) 8 P# V- d# s7 H, ?: o$ A; G

Microstrip versus Stripline

Microstrips are traces on the outer layer of a PCB,
as shown right.








Striplines are traces between two ground planes.
Striplines are less prone to emissions and susceptibility problems since the reference planes effectively shield the embedded traces. However, from the standpoint of high-speed transmission, the two parallel planes creates additional capacitance.

Regarding to LVDS signals, it is recommended the LVDS signals could be routed on microstrip transmission lines if possible.

Lumped versus Distributed System

Length of rising edge
l=rise time(ps)/medium delay(ps/in)

circuits size smaller than l/6 are lumped circuits, otherwise they are distributed circuits.

Ground Bounce

Ground bounce is crosstalk that occurs when there is a shift in the internal ground reference voltage due to output switching. This problem can result in erroneous state switching in ground-referenced (single-ended) gates. Essentially, transients on the ground disturb single-ended inputs that use the ground potential as a reference.
The ground and Vcc bounce cannot be eliminated, but providing low impedance, low inductance paths from the ground leads of the chip to the PCB ground can minimize their effects.
It is recommended that connecting each ground pin on a device directly to the PCB ground plane. Tying pins together and connecting them to the ground plane tends to increase inductance to ground and worsen ground bounce problems.

Decouple Circuit

-- to be continued --

Clamp Circuit

-- to be continued --

Latch-up Effect

-- to be continued --

Intersymbol Interference(ISI)

Refer to Wikipedia ISI article.

In telecommunication, intersymbol interference(ISI) is a form of distortion of a signal in which one symbol interferes with subsequent symbols. This is an unwanted phenomenon as the previous symbols have similar effects as noise, thus making the communication less reliable.

ISI is usually caused by multipath propagation and the inherent non-linear frequency response of a channel. ISI arises because of imperfections in the overall frequency response of the system.
The presence of ISI in the system introduces errors in the decision device at the receiver output. Therefore in the design of the transmitting and receiving filters, the objective is to minimize the effect of ISI.

Ways to fight against intersymbol interference include adaptive equalization and error correcting codes.

Multiplath Propagation
Multipath propagation means a wireless signal from a transmitter reaches the receiver via many different paths. The cuase of this include reflection, refraction and atmospheric effects. Since all of these paths are different lengths, this results in the different versions of the signal arriving at different times. This delay means that part or all of a given symbol will be spread into the subsequent symbols, thereby interfering with the correct detecting of those symbols. Additionally, the various paths often distort the amplitude and/or phase of the signal thereby causing further interference with the received signal.

Bandlimited Channels
A bandlimited channel means the frequency response is zero above or below a certain frequency(the cutoff frequency). Passing a signal through such a channel results in the removal of frequency component above and below this cutoff frequency.
This filtering of the transmitted signal affects the shape of the pulse that arrives at the receiver. Besides it is spread out over the subsequent symbol periods. When a message is transmitted through a channel, the spread pulse of individual symbol will interfere with following symbols.
As opposed to multipath propagation, bandlimited channels are present in both wired and wireless communications. The limitation is often imposed by the desire to operate multiple independent signals through the same area/cable; due to this, each system is typically allocated a piece of the total bandwidth available.
The bandlimiting can also be due to the physical properties of the medium.
Communication systems that transmit data over bandlimited channels usually implement pulse shaping to avoid interference caused by the bandwidth limitation. Often the channel response is not known beforehand, and an adaptive equalizer is used to compensate the frequency response.

TTL&CMOS

Abbreviation
TTL - Transistor-Transistor Logic
HTTL - High-speed TTL
LTTL - Low-power TTL
STTL - Schottky TTL
LSTTL - Low-power Schottky TTL
ASTTL - Advanced Schottky TTL
ALSTTL- Advanced Low-power Schottky TTL
CMOS - Complementary Metal Oxide Semiconductor
HC/HCT- High-speed CMOS Logic
AC/ACT- Advanced CMOS Logic
AHC/AHCT-Advanced High-speed CMOS Logic

1. TTL logic level
Voh > 2.4V; Vol < 0.4V; Normally, Voh ="3.5V"; Vol ="0.2V"; Vih>= 2.0V; Vil <= 0.8V. Noise margin = 0.4V.
2. CMOS logic level
Logic 1 level voltage approximate source voltage(VDD)
Logic 0 level voltage approximate 0V(GND)
CMOS logic has higher noise margin than TTL logic.

3. Level transform
Since TTL and CMOS have different logic level, a level transform circuit(voltage ladder) is needed while a TTL device connects to a CMOS device.

4. TTL and CMOS comparison
1). TTL circuit is a current control device; CMOS circuit is a voltage control device.
2). TTL circuit has higher speed, shorter propagation delay(5~10ns) but consume more power. CMOS has lower speed, longer propagation delay(25~50ns) but lower power consumption. The power consumption of CMOS circuit is relative to the frequency of the input signal. Higher frequency will consume more power and therefore generate more heat.

5. CMOS device latch-up effect
When the input current is too large, the current inside the CMOS device will be latched and get increased until power off or device damaged. Some measures we could apply to prevent this,
1). Add clamp circuit at both input and output to prevent exceeding rated voltage.
2). Add decouple circuit at power input to prevent high voltage pulse.
3). Add current-limiting resistor between VDD and source power.
4). While power on the system, power on CMOS device prior signal and load. And inverse sequence while power off.

6. CMOS device application note
1). CMOS device is a voltage control device, it has a large input impedance and good noise immunity. Therefore DO NOT floating unused pins, provide them a steady voltage level by a pull-high or a pull-low resistor.
2). While the input pins connect to a low impedance signal source, put current-limiting resistors in series between inputs and signal source to limit the input current under 1mA. The CMOS device could be damaged when input current over 1mA.
3). Add matching resistors while connect to a long signal path.
4). While a large capacitor exists at the input, add a protecting resistor between input and the capacitor. Rp=V/1mA, where V is the voltage on the capacitor.