TTL&CMOS

Abbreviation
TTL - Transistor-Transistor Logic
HTTL - High-speed TTL
LTTL - Low-power TTL
STTL - Schottky TTL
LSTTL - Low-power Schottky TTL
ASTTL - Advanced Schottky TTL
ALSTTL- Advanced Low-power Schottky TTL
CMOS - Complementary Metal Oxide Semiconductor
HC/HCT- High-speed CMOS Logic
AC/ACT- Advanced CMOS Logic
AHC/AHCT-Advanced High-speed CMOS Logic

1. TTL logic level
Voh > 2.4V; Vol < 0.4V; Normally, Voh ="3.5V"; Vol ="0.2V"; Vih>= 2.0V; Vil <= 0.8V. Noise margin = 0.4V.
2. CMOS logic level
Logic 1 level voltage approximate source voltage(VDD)
Logic 0 level voltage approximate 0V(GND)
CMOS logic has higher noise margin than TTL logic.

3. Level transform
Since TTL and CMOS have different logic level, a level transform circuit(voltage ladder) is needed while a TTL device connects to a CMOS device.

4. TTL and CMOS comparison
1). TTL circuit is a current control device; CMOS circuit is a voltage control device.
2). TTL circuit has higher speed, shorter propagation delay(5~10ns) but consume more power. CMOS has lower speed, longer propagation delay(25~50ns) but lower power consumption. The power consumption of CMOS circuit is relative to the frequency of the input signal. Higher frequency will consume more power and therefore generate more heat.

5. CMOS device latch-up effect
When the input current is too large, the current inside the CMOS device will be latched and get increased until power off or device damaged. Some measures we could apply to prevent this,
1). Add clamp circuit at both input and output to prevent exceeding rated voltage.
2). Add decouple circuit at power input to prevent high voltage pulse.
3). Add current-limiting resistor between VDD and source power.
4). While power on the system, power on CMOS device prior signal and load. And inverse sequence while power off.

6. CMOS device application note
1). CMOS device is a voltage control device, it has a large input impedance and good noise immunity. Therefore DO NOT floating unused pins, provide them a steady voltage level by a pull-high or a pull-low resistor.
2). While the input pins connect to a low impedance signal source, put current-limiting resistors in series between inputs and signal source to limit the input current under 1mA. The CMOS device could be damaged when input current over 1mA.
3). Add matching resistors while connect to a long signal path.
4). While a large capacitor exists at the input, add a protecting resistor between input and the capacitor. Rp=V/1mA, where V is the voltage on the capacitor.